The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed.
For example, a spacer technique is often used to form mandrels, which are used in devices such as a fin field effect transistor (FinFET) device. Frequently, the spacer technique is used for doubling the exposed pattern in advanced lithography. That is, the pitch of a final pattern is reduced to only half compared with the first exposed pattern. Due to constraints from the lithography process, it is difficult to obtain small cut features.
Also in some occasions, it is desirable to have a large process window. The process window refers to a range of focus and exposure settings that will still produce the desired features into the photo-resist layer in the photolithographic process.
Accordingly, what is needed is an improvement in this area.